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Description: 常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是全加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
Platform: |
Size: 1681408 |
Author: xiaobei |
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Description: 常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本文件是半加器模块
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
Platform: |
Size: 1486848 |
Author: xiaobei |
Hits:
Description: 常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本模块是3-8译码器（mutex_3to8）
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
Platform: |
Size: 1816576 |
Author: xiaobei |
Hits:
Description: 常用的VHDL模块，适合VHDL入门者，本系列一共包含六个VHDL模块，本模块是计算机运算器模块（S6）实现运算器相关功能
1.算术逻辑单元（alu_1706）,实现算术逻辑运算
2.CPU寄存器组（cpu_register），实现四个通用寄存器（具有读写功能），一个PC寄存器（清零，置数，加一计数，减一计数，工作使能）。
3.全加器（full_adder）
4.半加器（half_adder）
5.3-8译码器（mutex_3to8）
6.计算机运算器（S6）实现运算器相关功能-VHDL modules commonly used for VHDL beginners, this series contains a total of six VHDL module, arithmetic logic unit (alu_1706), implement arithmetic and logic
2.CPU register set (cpu_register), to realize the four general-purpose registers (read and write functions), a PC register (cleared, set the number, plus one count minus one count, work enabled).
3. The full adder (full_adder)
4. The half-adder (half_adder)
5.3-8 decoder (mutex_3to8)
6. Computer operator (S6) to achieve operator-related functions
Platform: |
Size: 2571264 |
Author: xiaobei |
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Description: 基于VHDL的CPU的设计，本科课程设计，实现了一个指令集，能计算加减乘。-CPU design VHDL-based undergraduate curriculum design and implementation of a set of instructions, subtraction, multiplication, can be calculated.
Platform: |
Size: 1951744 |
Author: |
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Description: this document descript the implementation os cpu microprocessor on fpga with vhdl code style and simulation on with modelsim.
Platform: |
Size: 105472 |
Author: j |
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Description: 用VHDL写的模拟cpu程序，可以下载到硬件完成仿真，东南大学课程设计-
Written in VHDL simulation CPU program, you can download to the hardware simulation, Southeast University curriculum design
Platform: |
Size: 922624 |
Author: 戴娜 |
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Description: 实现18位操作指令实现PC指针的变化，及得到对应地址的操作指令(Implement 18 bit operation instructions to realize change of pointer and obtain operation instructions corresponding to corresponding address)
Platform: |
Size: 8635392 |
Author: ltfy咖啡 |
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